The present invention relates generally to a method and system of linking on-chip parasitic coupling capacitance into distributed pre-layout passive models. In particular, the present invention relates to a method and system of linking on-chip parasitic coupling capacitance into distributed pre-layout passive models such as transmission lines and on-chip spiral inductors that accurately does so in a physically realistic manner.
On-chip passive models such as transmission lines (t-lines) are used for fast and accurate pre-layout estimation of high-frequency, critical interconnect configurations. A P-Cell draws the t-line layout and, through marker shapes, the Layout Versus Schematic (LVS) recognizes the t-line and calls the t-line “compact model”. The LVS blocks parasitic extraction from extracting the capacitance, resistance, and inductance of the t-line metals.
In the case of t-lines, conventionally, the parasitic networks of neighboring conductors are accounted for by t-line model input parameters. In the case of coplanar waveguides (CPWs), for example, the variable “plane” is used to account for the parasitic networks due to neighboring lines. Several CPW models can be hooked in series in order to adjust frequency and bandwidth to design specifications.
However, conventionally in transmission line models, all crossing metal, no matter how sparse, is treated as a full plane. This causes inaccuracies because of an overestimation of the capacitance. Thus, conventionally, there is no way to model on-chip layout parasitic capacitance interactions with distributed pre-layout t-line models. Nevertheless, parasitic coupling capacitance to a pre-layout t-line must be modeled in a distributed manner to correctly predict delay. This is important in any critical on-chip interconnect path, especially with respect to clock lines. In the case of on-chip spiral inductors, conventionally, either all crossing metal is modeled as either full planes or ignored completely. As in the case of transmission lines, this causes inaccuracies in high-performance on-chip distributed spiral inductor models.